Reason behind :-
All of the signals for the NAND Flash interface are used during boot by the CPU, even if only a smaller collection of these pins are used by the real Flash device itself. A customer might think that since some NAND Flash devices do not use (or even have the pins to connect) the four Ready/Busy signals RB1, RB2, RB3 or RB4, that these are free for use as GPIO pins; but this is not true during start-up. It is only after code execution has begun and initialized the Flash controller for the real flash devices that are fitted that these four pins become unallocated and therefore free for use as GPIO pins. The problem is that if a customer does not appreciate this and makes any of them to be input pins with a default state that is low (or has pull-down resistors to do the same thing) the result is that the Flash interface sees this signal during boot and thinks that it is part of the actual interface – and holding the line low causes wait-states to be added. Thus in that state, the boot process hangs and cannot be recovered.
Refer https://www.digi.com/resources/documentation/digidocs/pdfs/90001128.pdf page 36 >
The warning about NANDF_* pins especially for NANDF_RB0 to NANDF_RB3 (J2.177-J2.180) can be read as :-
'Must not be low during NAND boot: the CPU will add wait-states while this signal is low during boot – even if the NAND Flash does not support this function'